CV

PDF version of my CV can be found here.

Education

• B.S. in ECE,Zagazig University, 2016 - 2021

Work Experience

• ICpedia. (Jul 2022 - Sep 2020)
  • Responsible for Physical Implementation of an IP - starting from Netlist to GDS, including floorplanning, Placement, Clock design, Optimization, Timing closure, DRC/LVS, LEC, MVRC, and sign-off.
  • Analyzed Timing for blocks and fixed the timing violations.
  • Analyzed Clock slews and skews and optimized the clock tree for maintaining the slew and skew limits.
  • Used the concept of useful skew to fix timing violations for critical blocks.
• Military Conscription, Benha Electronics Co. (Dec 2021 - Dec 2022)
  • Design real-time digital signal processing systems
  • Analyze cost and risk factors involved in system development activities
• Synopsys (Spring 2021)
  • ASIC Physical Design Engineer
• Cadence. (Jan 2021)
  • ASIC Physical Design Engineer
• Arm Ltd (Dec 2020)
  • ASIC Design Engineer
• One Lab. (Aug 2020 - Nov 2020)
  • RTL to GDSII: going through digital design flow starting from Constraint, Synthesis, PnR steps, Timing, Sign off, and Physical verification.

Volunteer Experience

• 2019:2020 Former Project Management for Enactus ZU,
• 2018:2019 Former PR director for Hult Prize Foundation, ZU.

Skills

• Verilog/ VHDL
• LVS/ DRC/ Density rules
• C/ Python/ MATLAB