UPF Guide

3 minute read

Published: September 16, 2022

UPF in SOC:

1. Set the level of implementation constraints.

GENUS Training Notes

6 minute read

Published: August 20, 2022

The following is my notes of GENUS training course on Cadence’s training module

Difference between blocking and non blocking statements in Verilog

3 minute read

Published: April 15, 2022

Blocking and non-blocking are part of the procedural assignments in Verilog. Following are the differences between them:-

Constraining Multiplexed Data Ports

4 minute read

Published: March 15, 2022

• Question: I have data input and output ports that I would like to constrain against multiple clock domains. What’s the best way to do this?

Guidelines and recommendations for macro placement

4 minute read

Published: April 29, 2021

Problem:

What guidelines should I follow when placing hard macros in the floorplan?