ASIC Design training

Teaching assistant for ASIC design internship program @ Zagazig University. My role is to help trainees with design and implementation procedures and grade their lab reports.

PDF version of my Lab calss can be found here.

ASIC RTL-to-GDSII flow using Cadence

In this Course, you learn how to implement a design from RTL-to-GDSII using CadenceĀ® tools. You will start by coding a design in Verilog. You will simulate the coded design, followed by design synthesis and optimization. You will then run equivalency checks at different stages of the flow. After synthesizing the design, you will floorplan, and place-and-route the synthesized netlist while meeting timing. You will run a gate-level simulation throughout the flow. Finally, you will write out a GDSII file

My Lab calss can be found here