systolic array based Google TPU
This project implements a systolic array, from behavior level (RTL) to tape-out.
Posts by Collection
portfolio
SoC-Implementation of OpenMSP430 Microcontroller
This project implements a -OpenMSP430 tape-out.
ASIC Implementation UART
This repository presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals.
Mini-Stereo Digital Audio Processor MSDAP
This is a project of ASIC. MSDAP is a low-cost, low-power and application specific mini stereo digital audio processor used in a hearing aid. The main function of this processor is a two-channel, 256 order, finite impulse response (FIR) digital filter. It receives 16 bits voice data(sampled at 50 kHz) and computes the FIR result at the speed of 25.MHz.
RISC-V CPU
This project is a RISC-V CPU with 5-stage pipeline implemented in VHDL, synthesized and Placed in order to tape out.
talks
Talk 1 on Static timing analysis (STA)
Published:
Static timing analysis is instrumental in efficiently verifying a design’s temporal behavior to ensure correct functionality at the required frequency. This presentation addresses static timing analysis in the presence of crosstalk for circuits containing level-sensitive latches, and edge-trigger Flip-Flop, typical in high-performance designs.