Guidelines and recommendations for macro placement

4 minute read



What guidelines should I follow when placing hard macros in the floorplan?


This solution provides designers performing physical design (Place & Route) with tips and guidelines to create an initial floorplan. These guidelines will help you maximize the space available for standard cell placement, avoid routing congestion problems, and achieve the power supply routing requirements.

This solution focuses on two main areas to help you achieve high-density designs:

  • Macro Placement
  • Row Generation

These tips range from simple guidelines to more advanced ones that may or may not apply to your design. For your design, you also have to take into account specific conditions and constraints such as:

  • Timing
  • Clock
  • Power
  • IP specific restriction
  • DFT test

Tips for macro placement

  1. Place macros around chip periphery

If you do not have a rationale to place the macro inside the core area, place macros around the chip periphery. Placing a macro inside the core can invite serious consequences during routing due to a lot of detour routing. This is because macros are equal to a large obstacle for routing. Also, placing the hard macros around the core-periphery makes it easier to supply power to these macros, and reduces the chance of IR drop problems for macros consuming high amounts of power.


  1. Consider connections to fixed cells when placing macros When you decide the macro position, you have to pay attention to connections to fixed elements such as I/O and pre-placed macros. Place macros near the corresponding associate fixed elements. Check connections by displaying flight lines in the GUI.


  1. Orient macros to minimize the distance between pins When you decide the orientation of macros, you also have to take into account the positions of the pins and the respective connections.


  1. Reserve enough room around macros For regular net routing and power grid, you have to reserve enough routing space around macros. In this case, estimating routing resources with precision is very important. Use the congestion map from trialRoute to identify hotspots between macros and adjust the placement as needed.


  1. Reduce open fields as much as possible Except for reserved routing resources, remove dead space to increase the area for random logic. Choosing a different aspect ratio (if that option is available) can eliminate open fields.


  1. Reserve space for power grid The number of required power routes can change based on the power consumption. You have to estimate the power consumption and reserve enough room for the power grid. If you underestimate the space required for power routing, you can encounter routing problems.


Tips for ROW generation

  1. Remove rows around macros When you generate/adjust ROW, remove it to reserve routing resource. Another way to do this is to create block halos or placement blockages. This will improve not only the routing quality but also the placement quality. Use soft blockages between macros to avoid cells being placed in the channels. Buffers can be placed in the channels with soft blockages during CTS and timing optimization.


This guideline is for the initial floorplan. To optimize for timing, clock, and crosstalk, you sometimes have to regenerate the rows between blocks for buffer insertion.

  1. Avoid narrow channels between blocks (if possible) Narrow random areas between blocks can cause problems in CTS and routing. If possible, try to avoid narrow rows in between macros.


  1. Keep the aspect ratio of the random area close to 1.0 First, rectangular random logic is preferable over a polygon-shaped area. A square area to place random logic is most preferable to achieve high density. If the aspect ratio exceeds 4.0, the density you will achieve becomes much lower.


  1. Keep random areas continuous to avoid detaches areas If there are multiple random logic areas, the gate density will be lower. Clock handling also gets much more difficult. If possible, merge these areas together.



  1. Floorplanning is art
  2. Floorplanning concepte challenges and closure
  3. DVD Lecture 7: Standard Cell Placement