UPF Guide
Published:
UPF in SOC:
1. Set the level of implementation constraints.
Posts by Tags
ASIC Design
GENUS Training Notes
Published:
The following is my notes of GENUS training course on Cadence’s training module
Difference between blocking and non blocking statements in Verilog
Published:
Blocking and non-blocking are part of the procedural assignments in Verilog. Following are the differences between them:-
Constraining Multiplexed Data Ports
Published:
- Question: I have data input and output ports that I would like to constrain against multiple clock domains. What’s the best way to do this?
Guidelines and recommendations for macro placement
Published:
Problem:
What guidelines should I follow when placing hard macros in the floorplan?
LPD
UPF Guide
Published:
UPF in SOC:
1. Set the level of implementation constraints.
Placement
Guidelines and recommendations for macro placement
Published:
Problem:
What guidelines should I follow when placing hard macros in the floorplan?
PnR
GENUS Training Notes
Published:
The following is my notes of GENUS training course on Cadence’s training module
Guidelines and recommendations for macro placement
Published:
Problem:
What guidelines should I follow when placing hard macros in the floorplan?
RTL Design
Difference between blocking and non blocking statements in Verilog
Published:
Blocking and non-blocking are part of the procedural assignments in Verilog. Following are the differences between them:-
STA
Constraining Multiplexed Data Ports
Published:
- Question: I have data input and output ports that I would like to constrain against multiple clock domains. What’s the best way to do this?
Synthesis
GENUS Training Notes
Published:
The following is my notes of GENUS training course on Cadence’s training module
Constraining Multiplexed Data Ports
Published:
- Question: I have data input and output ports that I would like to constrain against multiple clock domains. What’s the best way to do this?
UPF
UPF Guide
Published:
UPF in SOC:
1. Set the level of implementation constraints.
Verilog
Difference between blocking and non blocking statements in Verilog
Published:
Blocking and non-blocking are part of the procedural assignments in Verilog. Following are the differences between them:-