Blocking and non-blocking are part of the procedural assignments in Verilog. Following are the differences between them:-

• A blocking statement will not block the execution of the statement that is in a parallel block, means it will execute sequentially while Nonblocking assignment allows scheduling of assignment that are executed in a sequential block.

• A blocking statement is a one-step process i.e evaluate the RHS of the expression and update the LHS without any delay while Nonblocking is a two-step process i.e.

  • a) Evaluate the RHS expression at the beginning of the time step and
  • b) Update the LHS at the end of the time step.

Let’s take an example with some delay:-

• Blocking:-

always @(posedge clk) 
begin 
 x = 1; // Evaluate and assign x  
 #10; 
 y = x + 1; //wait for 10 time units   then evaluate and assign 
end

• Nonblocking:-

always @(posedge clk) 
 begin 
  x <= 1; //Evaluate x but update it only at the end of time step 
  #10; 
  y <= x + 1; //wait for 10 time units then evaluate and then update/assign it at the end of time step. 
 end

• Blocking statements are executed in the Active region of Verilog Stratified Event Queue while Evaluation of RHS of Nonblocking statement occurred in Active Region and update of LHS side happens in NBA region.

The stratified Event Queue of Verilog will look like:-

• Blocking assignment always suffers from the problem of Race condition when the assignment happens to it from two processes concurrently. While in the Nonblocking statement, there is no such problem since the updated value is assigned after the time step.

Let’s take an example to illustrate the problem:-

• Blocking:-

always @(posedge clk) 
 X = y; 
always @(posedge clk)  
 y = x; 

Any one of the above always blocks can be executed in any order and instead of swapping the values both the register will get updated with the same value which is a race condition.

• Nonblocking:-

always @(posedge clk) 
 x <= y; 
always @(posedge clk) 
 y <= x; 

So in the case of Nonblocking at the pos edge of the clock, the values of all RHS are evaluated and stored in a register, and then at the end of the time step the values stored in the register are assigned to LHS, and because of that, the values of x and y are swapped correctly.

While Modelling combinational logic, blocking statements are preferred while for sequential logic, nonblocking statements are always used.

To explain let’s take an example of simple SISO.

• Using Blocking:-

always @(posedge clk) 
 begin  
  q1 = d; 
  q2 = q1; 
  q3 = q2;  
 end 

Now when you synthesized this code it wouldn’t result in a 4 bit SISO as above, instead, it will result in a single Flip Flop where q4 = d.

• Using Non-Blocking:-

always @(posedge clk) 
 begin 
  q1 <= d; 
  q2 <= q1; 
  q3 <= q2;  
 end 

And when you synthesize the above code the actual SISO of each stage output you will get as above.

• Blocking statements can be used in initial, always blocks, and assign statements while Nonblocking can only be used in initial and always block but assign statements can not be used

BIBLIOGRAPHIC NOTES

• 1- Blocking and Nonblocking Assignment

• 2- Blocking and Non-blocking Assignments in Explicit and Implicit Style Verilog Synthesis by Mark ArnoldJerry,J CupalJames, andd D Shuler